The present invention relates to the field of semiconductor processing, and, more particularly, to a method for making a high quality oxide for a semiconductor device.
Semiconductor devices in the form of integrated circuits are widely used in most electronic devices. For example, computers, cellular telephones, and other similar devices typically include one or more integrated circuits (ICs). In addition, many typical types of ICs are based upon metal-oxide semiconductor (MOS) technology wherein each transistor includes doped source and drain regions in a semiconductor substrate, with a channel region between the drain and source. An oxide layer also referred to as the gate oxide layer is a thin insulating layer of silicon oxide formed over the channel region and which separates the channel region from an overlying conductive gate. The gate may be a metal or doped polysilicon layer, for example.
As device dimensions have been reduced in semiconductor processing, the quality of the gate oxide has become even more important. One technique used to fabricate the gate oxide is thermal oxidation. The thermally grown oxide provides good electrical performance, provides improved mechanical bonding to the underlying silicon substrate, and helps to block ion implantation and diffusion of dopants into the channel region.
There have been considerable efforts directed to forming high quality oxides for semiconductor devices. For example, an article entitled xe2x80x9cImprovement of Gate Dielectric Reliability for p+ Poly MOS Devices Using Remote PECVD Top Nitride Deposition on Thin Gate Oxidesxe2x80x9d by Wu et al. in the IEEE 36th Annual International Reliability Physics Symposium, Reno Nev. 1998, pp. 70-75, discloses a dual layer dielectric including a nitride portion on a thin thermally grown oxide. The introduction of nitrogen atoms into the gate dielectric may suppress diffusion of boron atoms from heavily doped p+ polycrystalline silicon gate electrodes, and reduce defect generation under either Fowler-Nordheim stressing or hot carrier stressing. Along these lines, U.S. Pat. No. 5,891,809 to Chau et al. discloses a method for forming a nitrided oxide layer wherein a substrate is oxidized in a chlorinated dry oxidation ambient followed by a low temperature pyrogenic steam oxidation. A low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.
U.S. Pat. No. 5,869,405 to Gonzalez et al. discloses in situ rapid thermal etching and oxidation to form an oxide. In particular, an oxidation step is followed by an etch step to remove contamination and damage from the substrate. Repeated in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is achieved.
U.S. Pat. No. 5,81,892 to Lojek et al. discloses a method for making an oxide including both pre- and post-oxidation anneal steps. The patent provides that the anneals, the ambients selected, and various cleaning steps help ensure a high quality gate or tunnel oxide. A portion of the oxide layer grown during the high temperature (1000xc2x0 C.) anneal and subsequent cool down is desirably reduced to less than about 20 xc3x85, and its growth is the necessary byproduct of incorporating oxygen into the oxide bulk for the benefit of improving electrical performance. The oxide layer is described as having an overall thickness of 100 xc3x85.
Silicon dioxide is not a good diffusion barrier for gate electrode dopants, such as boron. Even with nitrogen incorporation, ultrathin nitrided oxides cannot be used for sub-0.25 xcexcm technologies due to a high tunneling current and a rough Si/SiO2 interface. Recent predictions of the end of gate-oxide scaling have got the industry""s undivided attention. This has led to an intensive search for alternative gate dielectrics, such as Ta2O5, that have the potential to significantly ameliorate this problem. However, these materials suffer from unacceptable levels of interface traps (Dit), bulk fixed charge (Qf), low interface carrier mobility and phase stability issues. Hence, a significant silicon-dielectric interface engineering is needed before high dielectric constant (high-k) can be used as gate material in complementary metal-oxide-semiconductor (CMOS) technologies. It is widely accepted that there are very significant challenges in both the materials science and the process architecture before an alternative dielectric can be used commercially. At this point the industry is directing a concerted effort at the extension of SiO2 for as long as possible.
The Semiconductor Industry Association (SIA) has recently published its latest roadmap, which presents projections of the expected device and manufacturing process requirements covering the next 15 years. The MOS-style transistor is expected to continue to provide the most important electronic element for the near future, but the end of the ability to scale down devices using conventional MOS technology is approaching. Several key device fabrication methods will not be applicable when device dimensions shrink below 0.1 m. Lithography for features 0.1 xcexcm poses a serious economic problem, but a more fundamental problem arises when the gate oxide thickness drops below about 25 xc3x85, because of the large leakage currents associated with direct tunneling through such a thin oxide.
Aggressive scaling of oxide thickness for future CMOS logic requires, among other concerns, an assurance that the oxide can meet requirements for reliability. When an electron current is established across the gate dielectric (SiO2) of a MOS capacitor or transistor, defects such as electron traps, interface states, positively charged donor-like states, etc., adversely impact the oxide until a point where the oxide suddenly and destructively breaks down. The exponentially increasing tunnel current with decreasing oxide thickness will cause the time-to-breakdown to decrease if the gate voltage is not simultaneously reduced sufficiently.
The rate of defect generation by electrical stress in silicon dioxide has been measured as a function of gate voltage down to 2 V on a variety of MOSFETs with oxide thickness in a range of 1.4 to 5 nm. The critical defect density necessary for destructive breakdown has also been measured in this thickness range. These quantities are used to predict time to breakdown for ultrathin oxides at low voltages. The properties of the break-down distribution, which becomes broader as the oxide thickness is reduced, are used to provide reliability projections for the total gate area on a chip. It has been predicted that oxide reliability may limit oxide scaling to about 2.6 nm (CV extrapolated thickness) of 2.2 nm (QM thickness) for a 1 V supply voltage at room temperature and the current SIA roadmap will be unattainable for reliability reasons by sometime early next century.
Unfortunately, despite continuing efforts and developments in the area of forming high quality oxides, device performance and longer term reliability is still compromised by conventional gate oxides, especially as device dimensions continue to be reduced.
What is needed, therefore is a method for making a high quality oxide layer for a semiconductor device that overcomes the shortcomings of conventional oxide fabrication techniques.
The present invention is drawn to a method for making a graded oxide layer by growing a first oxide portion on a substrate by upwardly ramping the substrate to a first temperature lower than the SiO2 viscoelastic temperature (also referred to as the glass transition temperature), and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Modulated heating and cooling segments of the process are employed and are thought to reduce the stress of the oxide of the present invention. A second oxide portion is then grown between the first oxide portion and the substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature for a second time period. In one embodiment the first and second oxide portions are grown so that the second oxide portion has a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.
The method produces an oxide layer having graded portions with greatly reduced stress, and substantially higher reliability, among other desirable properties. The ratio of the relative thicknesses of the first and second portions can be controlled to produce an ultrathin oxide layer, for example, with the advantageous properties discussed above.